PMOS Transistor
Fabrication
Eleven labs, four photomasks, and one ruined evaporator run to turn bare silicon into a working p-n junction.
Starting Material
ENGR 430 (Semiconductor Device Fabrication, Fort Lewis College, Spring 2026) is an eleven-lab cleanroom sequence that carries a bare silicon wafer through a full PMOS transistor process flow. Every wafer started identical: 2" phosphorus-doped n-type [100] silicon, 3–9 Ω·cm resistivity, 280 ± 25 µm thick.
Lab 1 is entirely about knowing that starting point cold, wafer handling and cleaning technique, then a four-point probe resistivity measurement (1 mA test current) to confirm each wafer actually falls inside spec before a single process step touches it.
Drying the wafer post-clean with the N₂ gunField Oxide Growth
The field oxide (FOX) that will isolate devices is grown with a dry-wet-dry (DWD) thermal cycle, modeled with the Deal-Grove equation. We only adjusted the first dry-cycle time, 65 and 75 minutes across two runs, and used the model to predict a resulting oxide thickness of 3300 Å.
The ellipsometer and a cleaved SEM cross-section told a different story: real oxide thickness measured ~1.1 µm (11,000 Å), over three times the Deal-Grove prediction. A large FOX isn't necessarily bad (it buys margin against over-etching later), but it's a real gap between the model and the furnace worth flagging rather than quietly rounding away.
Oxidation/diffusion furnace, thermal block
SEM cross-section, measured FOX: 1.19 µmFour Photomasks, One Routine
Every patterning step in this process (active area, gate strip, contact openings, and final metal) runs the same core routine on a Karl Süss contact aligner: spin coat photoresist, soft bake, align to the previous layer, expose under UV (dose calculated from a measured lamp intensity, not a fixed timer), develop, wet-etch with buffered oxide etch (BOE), then strip the resist.
Mid-semester we adjusted the spin speed from 3000 to 5000 RPM for a thinner, more uniform resist coat, and changed our Karl Süss alignment habits to stop the wafer from shifting during exposure, both fixes are now baked into the standard procedure for the next class.
Karl Süss aligner, measuring UV lamp intensity
Chromium photomask, dark-field patternSpin-On Dopant & Drive-In
With the active area opened, a spin-on dopant (SOD) is applied and driven into the exposed silicon in two thermal steps, a short, high-concentration predeposition followed by a longer drive-in that pushes the dopant to its target junction depth. Wafers were laid flat and parallel in the quartz boat, not stood on edge, and kept to four per furnace run for even heating.
Same story as the field oxide: predicted diffusion-oxide thickness was 1080 Å, SEM measured 2100 Å. Working backward from that, we estimated a real BOE etch rate of about 518.5 Å/min for this step and now build in a 15% over-etch to cover wafer-to-wafer variation. A separate spin-on dopant removal step (Lab 5) then strips the SOD layer before moving on to the gate mask.
Gate Region Strip & Reoxidation
Mask 2 strips the oxide back off the gate region, and a second, thinner oxidation regrows a dedicated gate oxide in its place. Expected thickness from the process model was 500–600 Å; the ellipsometer measured 680–740 Å across our runs, closer than the field oxide gap, but still consistently thicker than modeled, which tracks with everything else we saw from this furnace.
Metallization
After Mask 3 opens the contact windows, aluminum needs to land on the wafer to form ohmic contacts. This lab is where the semester's biggest detour happened.
Our first choice was the thermal evaporator. Run one finished, but a carbon deposit inside the tool, leftover from it sitting unused, vaporized along with the aluminum and contaminated the film. Run two was worse: the diffusion pump's chiller lines failed mid-deposition and started leaking water. We killed the bias and vented the chamber immediately, but the exposed aluminum oxidized into a hard, sapphire-like layer. Every sample from both evaporator runs had its aluminum etched back off and started over.
We moved to the lab's Denton Desktop Pro DC sputter coater instead. The first sputter attempts came out with a visibly non-uniform, cloudy aluminum film, which took several runs of parameter tuning to chase down. The settings that finally gave a clean, even film: 60 W DC power, 2 mTorr argon working pressure (5N purity), pumped to a 5×10⁻⁶ Torr base pressure before deposition, run for ~40 minutes.
Denton Desktop Pro, DC power panel
Argon / N₂ / compressed air supply valvesThe payoff: a fully metallized wafer, aluminum landing clean and even across all nine dies.
Post-metallization, all nine dies, evenly coatedDevice Analysis
After Mask 4 patterns the aluminum into isolated contacts, every die carries a set of test structures alongside the transistors: resistors, contact-resistance chains, p-n junction diodes, MOS capacitors, and the PMOS devices themselves. All of it gets probed on an HP4145B Semiconductor Parameter Analyzer for I-V and C-V characteristics, and a cleaved cross-section goes under the SEM for a direct physical check against what the electrical measurements imply.
Comb structure under the probe station
Serpentine resistor structures, post metal-etchThe HP4145B's CRT plot came through loud and clear on the diode structures, clean forward I-V curves that behave like the ideal diode equation predicts.
HP4145B: diode forward I-V curve (run 1)
HP4145B: diode forward I-V curve (run 2)Honest result: this run produced a working p-n junction diode with measurable, well-behaved I-V curves, not a fully functional PMOS transistor. Between the evaporator losses and the discrepancies compounding from oxidation through diffusion, the three-terminal devices didn't come out clean enough to characterize as transistors by the end of the semester. The diode structures did, and that's a real, physically verified p-n junction built by hand through all eleven labs.
Dr. Jeff Jessing, Fort Lewis College
Hunter Goggin, Daniella Masha, Luke Bray
Original lab manual developed by the Fort Lewis College 2024–25 Engineering Senior Seminar team: Sahra Genc, Ian Van Horn, Leif Gislason, Jade Martinez, Natalia Lambos, Lincoln Scheer, and Eric Hill. Revised for accuracy and clarity by the Spring 2026 ENGR 430 cohort based on our own run through the process.